As recent rapid trend in modern electronic devices is not only toward thinner, lighter and smaller devices, but also toward multifunctional and high-performance devices, the fabrication and technology of integrated circuits (ICs) has to evolve correspondingly toward a more high-density and miniature design so as to allow more electronic components to be received inside limited chip space. Consequently, the relating IC package substrate and the package technology are evolved accordingly to meet the trend.
FIG. 1 illustrates a package structure 10 commonly used in the art of molded interconnection substrate (MIS). The package structure 10 formed on a substrate 11 includes a lower-layer wiring 12, an upper-layer wiring 14, copper pillars 18 connecting the lower-layer wiring 12 and the upper-layer wiring 14, and a molding compound layer 16 covering the lower-layer wiring 12 and surrounding the copper pillars 18. Wherein, the molding compound layer 16 is made of a rigid material which is fragile after curing, so that the package structure 10 is subject to damage in its fabrication process. Also, the forming material of the molding compound layer 16 is not compatible with metal such as copper, and this may deteriorate the reliability of the upper-layer wiring 14. Even though a photo-sensitive material such as primer, can be coated on the molding compound layer 16 to facilitate the formation of the upper-layer wiring 14, the package structure 10 is subject to fragility and thus low product yield. Therefore, it is in need of a new and advanced packaging solution.